Sense amplifier and data sensing method thereof

ABSTRACT

A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a reference memory cell, respectively; enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to a sense amplifier, and moreparticularly to a sense amplifier for amplifying a sensing voltage and areference voltage via a latch circuit.

2. Description of the Related Art

In the modern age having the technology changing with each passing day,a non-volatile memory, such as a flash, is widely used in variouselectronic products. Conventionally, when storage data recorded in amemory cell of the flash is to be read, the memory cell is biasedthrough a column decoder and a row decoder so that the memory cellgenerates a sensing current. Thereafter, the sensing current is comparedwith a reference current through a sense amplifier so that the storagedata can be judged.

With the technological development which changes with each passing day,the sensing current of the flash is reduced in the more advancedmanufacturing technique so that the flash has the lower powerconsumption and the higher access speed. However, the lower sensingcurrent causes the sense amplifier to have the smaller sensing margin sothat the sense amplifier tends to obtain the incorrectly stored data.Therefore, it is an important subject in the industry to develop thetechnology capable of effectively enhancing the data sensing accuracy ofthe sense amplifier.

SUMMARY OF THE INVENTION

The invention is directed to a sense amplifier and a data sensing methodthereof, wherein the sense amplifier of the invention advantageously hasthe higher data sensing accuracy than the conventional sense amplifier.

According to a first aspect of the present invention, a sense amplifierfor sensing storage data stored in a memory cell of a memory isprovided. The sense amplifier includes a sensing node, a reference node,first and second bias circuits, first and second transmission circuitsand a latch circuit. The first bias circuit biases the sensing node to afirst voltage in response to a first control signal. The second biascircuit biases the reference node to the first voltage in response tothe first control signal. The first transmission circuit discharges thesensing node via the memory cell. The second transmission circuitdischarges the reference node via a reference memory cell. The latchcircuit amplifies a voltage difference between the sensing node and thereference node.

According to a second aspect of the present invention, a data sensingmethod for sensing storage data stored in a memory cell of a memory isprovided. The data sensing method includes the following steps. First, asensing node and a reference node are biased to a first voltage inresponse to a first control signal. Then, the sensing node is dischargedvia the memory cell, and the reference node is discharged via areference memory cell. Next, a latch circuit is enabled to amplify avoltage difference between the sensing node and the reference node.

The invention will become apparent from the following detaileddescription of the preferred but non-limiting embodiments. The followingdescription is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a sense amplifier according to afirst embodiment of the invention.

FIG. 2 is a timing chart showing signals associated with the senseamplifier of FIG. 1.

FIG. 3 is a flow chart showing a data sensing method according to thefirst embodiment of the invention.

FIG. 4 is a circuit diagram showing a sense amplifier according to asecond embodiment of the invention.

FIG. 5 is a timing chart showing signals associated with the senseamplifier of FIG. 4.

FIG. 6 is a flow chart showing a data sensing method according to thesecond embodiment of the invention.

FIG. 7 is a circuit diagram showing a sense amplifier according to athird embodiment of the invention.

FIG. 8 is a circuit diagram showing a sense amplifier according to afourth embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION First Embodiment

FIG. 1 is a circuit diagram showing a sense amplifier 10 according to afirst embodiment of the invention. FIG. 2 is a timing chart showingsignals associated with the sense amplifier of FIG. 1. As shown in FIGS.1 and 2, the sense amplifier 10 senses storage data stored in a memorycell (not shown) of a memory (not shown) according to a cell currentIcell provided by the memory cell of the memory (not shown).

The sense amplifier 10 includes a sensing node NDs, a reference nodeNDr, bias circuits 12 a, 12 b, 18 a and 18 b, transmission circuits 14 aand 14 b and a latch circuit 16. The bias circuit 12 a and thetransmission circuit 14 a are electrically connected to the sensing nodeNDs, the bias circuit 12 b and the transmission circuit 14 b areelectrically connected to the reference node NDr, and the latch circuit16 is electrically connected to the sensing node NDs and the referencenode NDr. The voltage on the sensing node NDs is a sensing voltage Vs,while the voltage on the reference node NDr is a reference voltage Vr.For example, the data stored in the memory cell is 0 and thecorrespondingly curve of the sensing voltage Vs is shown in FIG. 2.

The bias circuits 12 a and 12 b are enabled in response to an enabledlevel of a control signal Vddpul to respectively bias the sensingvoltage Vs and the reference voltage Vr to voltages approaching avoltage Vdd. For example, the voltage Vdd is a circuit high voltage ofthe sense amplifier 10, and the control signal Vddpul has the enabledlevel in an active period Ta.

For example, the bias circuits 12 a and 12 b respectively include P-typemetal oxide semiconductor (PMOS) transistors Tb1 and Tb2. The PMOStransistor Tb1 has a source for receiving the voltage Vdd, a drainelectrically connected to the sensing node NDs and a gate for receivingthe control signal Vddpul. The PMOS transistor Tb2 has a source forreceiving the voltage Vdd, a drain electrically connected to thereference node NDr and a gate for receiving the control signal Vddpul.The PMOS transistors Tb1 and Tb2 are enabled in response to the enabledlevel of the control signal Vddpul to respectively bias the sensingvoltage Vs and the reference voltage Vr to the voltages approaching thevoltage Vdd. For example, the enabled level of the control signal Vddpulis a signal low level.

The bias circuits 18 a and 18 b are enabled in response to an enabledlevel of a control signal Hvpul to respectively bias the sensing voltageVs and the reference voltage Vr to voltages approaching a voltage HV.The voltage HV has a level higher than a level of the voltage Vdd. Inthis embodiment, the levels of the voltages HV and Vdd are 5V (volts)and 2.8V, for example, and the control signal Hvpul has the enabledlevel in an active period Tb.

For example, the bias circuits 18 a and 18 b respectively include PMOStransistors Tb3 and Tb4. The operations of the PMOS transistors Tb3 andTb4 are similar to those of the PMOS transistors Tb1 and Tb2. The PMOStransistors Tb3 and Tb4 are enabled in response to the enabled level ofthe control signal Hvpul to respectively bias the sensing voltage Vs andthe reference voltage Vr to the voltages approaching the voltage HV. Theenabled level of the control signal Hvpul is a signal low level, forexample.

The transmission circuits 14 a and 14 b respectively receive the cellcurrent Icell generated by the memory cell and a reference current Irefgenerated by a reference memory cell (not shown) and respectivelyprovide the cell current Icell and the reference current Iref to thesensing node NDs and the reference node NDr. Thus, the sensing voltageVs is discharged via the cell current Icell, and the reference voltageVr is discharged via the reference current Iref.

For example, the transmission circuits 14 a and 14 b respectivelyinclude N-type metal oxidation semiconductor (NMOS) transistors Tt1 andTt2. The NMOS transistor Tt1 has a source for receiving the cell currentIcell, a drain coupled to the sensing node NDs and a gate for receivinga control signal VbIr. The NMOS transistor Tt2 has a source, which iscoupled to the reference memory cell (not shown) and receives thereference current Iref provided therefrom, a drain coupled to thereference node NDr and a gate for receiving the control signal VbIr. TheNMOS transistors Tt1 and Tt2 are enabled in response to the enabledlevel of the control signal VbIr to respectively provide the cellcurrent Icell to discharge the sensing voltage Vs, and provide thereference current Iref to discharge the reference voltage Vr.

Preferably, in an active period Tc when the sensing voltage Vs isdischarged via the cell current Icell provided by the NMOS transistorTt1 and the reference voltage is discharged via the reference currentIref provided by the NMOS transistor Tt2, the NMOS transistors Tt1 andTt2 are continuously biased to saturation region of the transistors.Consequently, the NMOS transistor Tt1 is biased to provide the stablecell current Icell to discharge the sensing voltage Vs. The NMOStransistor Tt2 is biased to provide the stable reference current Iref todischarge the reference voltage Vr.

More specifically, it is better to ensure that the NMOS transistors Tt1and Tt2 operate in the saturation region in the active period Tc.Consequently, the voltage HV has to be designed according to theconditions mentioned hereinabove so that the sensing voltage Vs and thereference voltage Vr are respectively substantially greater than thevoltages Vcell and Vrcell.

In this embodiment, the voltages Vcell and Vrcell substantially approach2.1V in the active period Tc, the sensing voltage Vs is discharged froma voltage approaching 5V to a voltage approaching 3.5V via the cellcurrent Icell, and the reference voltage Vr is discharged from a voltageappraching 5V to a voltage approaching 3V via the reference currentIref. Consequently, the transistors Tt1 and Tt2 may be biased to thesaturation region in the active period Tc.

The latch circuit 16 is enabled in response to enabled levels of controlsignals “latch” and “latchb” to amplify a voltage difference between thesensing voltage Vs, which is obtained after the discharge via the cellcurrent Icell, and the reference voltage Vr, which is obtained after thedischarge via the reference current Iref. Thus, the storage data can beobtained by comparing the amplified voltage difference between thesensing voltage Vs and the amplified reference voltage Vr. In thisembodiment, the control signals “latch” and “latchb” have the enabledlevels in an active period Td, for example.

For example, the latch circuit 16 includes transistors Tp1 and Tp2 andinverters 16 a and 16 b. The inverter 16 a includes an input terminalNDi1, an output terminal NDo1 and two power input terminals (not shown).The input terminal NDi1 and the output terminal NDo1 of the inverter 16a are respectively coupled to the sensing node NDs and the referencenode NDr, and the two power input terminals of the inverter 16 a arerespectively coupled to nodes NDp and NDn. The inverter 16 b has aninput terminal NDi2, an output terminal NDo2 and two power inputterminals (not shown). The input terminal NDi2 and the output terminalNDo2 of the inverter 16 b are respectively coupled to the reference nodeNDr and the sensing node NDs, and the two power input terminals of theinverter 16 b are respectively coupled to the nodes NDp and NDn.

The transistor Tp1 is, for example, a PMOS transistor having a sourcefor receiving the voltage Vdd, a drain coupled to the node NDp and agate for receiving the control signal “latchb”. The transistor Tp1 isenabled in response to the enabled level of the control signal “latchb”to provide the voltage Vdd to the node NDp. The transistor Tp2 is, forexample, a NMOS transistor having a source for receiving a voltage Vss,a drain coupled to the node NDn and a gate for receiving the controlsignal “latch”. The transistor Tp2 is enabled in response to the enabledlevel of the control signal “latch” to provide the voltage Vss to thenode NDn.

In this embodiment, the control signals “latch” and “latchb” are inversesignals, and the enabled levels of the control signals “latch” and“latchb” are respectively a signal high level and a signal low level.Consequently, the transistors Tp1 and Tp2 are enabled in the activeperiod Td when the control signals “latchb” and “latch” simultaneouslyhave the enabled levels in order to provide the voltage Vdd to the nodeNDp and provide the voltage Vss to the node NDn in response to thecontrol signals “latchb” and “latch”, respectively. Consequently, theinverters 16 a and 16 b of the latch circuit 16 form a circuit loop inthe active period Td so that the latch circuit 16 is enabled and thevoltage difference between the sensing voltage Vs and the referencevoltage Vr may be amplified.

The sense amplifier 10 of this embodiment further has storage capacitorsCs and Cr, which have first terminals respectively coupled to thesensing node NDs and the reference node NDr, and second terminals forreceiving the voltage Vss, wherein the voltage Vss is a ground voltage,for example. The storage capacitors Vs and Cr temporarily store thesensing voltage Vs and the reference voltage Vr. In this embodiment, thestorage capacitors Cs and Cr may also be omitted from the senseamplifier 10, and the sensing voltage Vs and the reference voltage Vrare temporarily stored directly in an equivalent parasitic capacitor,which is viewed from the sensing node NDs, and an equivalent parasiticcapacitor, which is viewed from the reference node NDr.

In this illustrated embodiment, the latch circuit 16 includes thetransistors Tp1 and Tp2, which are respectively enabled in response tothe control signals “latchb” and “latch” to respective provide thevoltages Vdd and Vss to the inverters 16 a and 16 b to enable the latchcircuit 16. However, the latch circuit 16 of this embodiment is notrestricted to the condition wherein the transistors Tp1 and Tp2 aresimultaneously included to enable the latch circuit 16. For example, oneof the transistors Tp1 and Tp2 may also be omitted from the latchcircuit 16 of this embodiment so that the latch circuit 16 is enabledonly via one of the control signals “latchb” and “latch”.

In this illustrated embodiment, the data stored in the memory cell isexemplified to be 0. However, the data stored in the memory cell is notlimited to be 0. For example, when the data stored in the memory cell is1, the correspondingly voltage variation is illustrated as curve Vs′shown in the FIG. 2.

FIG. 3 is a flow chart showing a data sensing method according to thefirst embodiment of the invention. Referring to FIG. 3, the data sensingmethod for sensing the storage data stored in the memory cell accordingto the embodiment of the invention includes the following steps. First,as shown in step (a), the bias circuits 12 a and 12 b respectively biasthe sensing voltage Vs on the sensing node NDs to the voltage Vdd andbias the reference voltage Vr on the reference node NDr to the voltageVdd in response to the enabled level of the control signal Vddpul in theactive period Ta. Next, as shown in step (b), the bias circuits 18 a and18 b respectively bias the sensing voltage Vs to the voltage HV and biasthe reference voltage Vr to the voltage HV in response to the enabledlevel of the control signal Hvpul in the active period Tb.

Then, as shown in step (c), the transmission circuit 14 a provides thecell current Icell to discharge the sensing voltage Vs, and thetransmission circuit 14 b provides the reference current Iref todischarge the reference voltage Vr in the active period Tc. Thereafter,as shown in step (d), the latch circuit 16 is enabled in response to theenabled levels of the control signals “latchb” and “latch” to amplifythe voltage difference between the sensing voltage Vs and the referencevoltage Vr in the active period Td.

In the step (d) of the data sensing method according to this embodiment,although the latch circuit 16 is enabled in response to the enabledlevels of the control signals “latchb” and “latch”, the latch circuit 16may also be simply modified such that the latch circuit 16 can operatein response to only one of the control signals “latchb” and “latch” inthe step (d) of this embodiment.

The sense amplifier of this embodiment amplifies the voltage differencebetween the sensing voltage and the reference voltage through the latchcircuit. Thus, the sensing margin of the sense amplifier of thisembodiment becomes larger. Consequently, even if the sensing current ofthis embodiment and that of the prior art have the similar values, thesense amplifier of this embodiment still has the advantage of the higherdata sensing accuracy.

In addition, the sense amplifier of this embodiment biases the sensingvoltage and the reference voltage to the voltages having the levelssubstantially higher than the circuit high voltage through two biascircuits. Therefore, the transistors for discharging the sensing voltagevia the sensing current and discharging the reference voltage via thereference current may be effectively biased to the saturation region sothat the values of the sensing current and the reference currentsubstantially become stable. Consequently, the sense amplifier of thisembodiment is free from the deviations of the reference voltage and thesensing voltage caused by the unstable values of the sensing current andthe reference current and thus the error storage data detected accordingto the reference voltage and the sensing voltage having the leveldeviations.

Second Embodiment

FIG. 4 is a circuit diagram showing a sense amplifier 20 according to asecond embodiment of the invention. FIG. 5 is a timing chart showingsignals associated with the sense amplifier of FIG. 4. The differencebetween the sense amplifier 20 of this embodiment and the senseamplifier 10 of the first embodiment is that the sensing node NDs isconnected to the input terminal NDi1 of a latch circuit 26 via a switchcircuit SW1, and the reference node NDr is connected to the inputterminal NDi2 of the latch circuit 26 via a switch circuit SW2. Theswitch circuits SW1 and SW2 may be switched so that the sensing voltageVs on the sensing node NDs and the reference voltage Vr on the referencenode NDr may be isolated from the amplified voltages of the latchcircuit 26.

The switch circuit SW1 is connected between the nodes NDs and NDi1, andthe switch circuit SW2 is connected between the nodes NDr and NDi2. Theswitch circuits SW1 and SW2 are enabled in response to an enabledcontrol signal C1 to respectively provide the sensing voltage Vs to thenode NDi1 and provide the reference voltage Vr to the node NDi2. In thisembodiment, the switch circuits SW1 and SW2 are PMOS transistors, andthe control signal C1 has the enabled level (i.e., the low signal level)in an active period Tc′ of the active period Tc, for example.Consequently, in the active period Td after the active period Tc, thelatch circuit 26 can amplify the voltage difference between the sensingvoltage Vs and the reference voltage Vr.

FIG. 6 is a flow chart showing a data sensing method according to thesecond embodiment of the invention. Referring to FIG. 6, the differencebetween the sensing methods of the second and first embodiments is thatthe method further includes a step (e) between the steps (c) and (d). Inthe step (e), the switch circuits SW1 and SW2 provide the sensingvoltage Vs on the sensing node NDs and the reference voltage Vr on thereference node NDr to the latch circuit 26 in response to the enabledlevel of the control signal C1.

Third Embodiment

FIG. 7 is a circuit diagram showing a sense amplifier 30 according to athird embodiment of the invention. Referring to FIG. 7, the differencebetween the sense amplifier 30 of the third embodiment and the senseamplifier 10 of the first embodiment is that the bias circuits 18 a and18 b, which respectively rise the sensing voltage Vs and the referencevoltage Vr to the voltage HV, are omitted from the sense amplifier 30,and the sensing voltage Vs and the reference voltage Vr are respectivelyset only via bias circuits 32 a and 32 b for respectively rising thesensing voltage Vs and the reference voltage Vr to a voltage Vdd′.

In this embodiment, the level of the voltage Vdd′ preferably makes thetransistor Tt1′ and Tt2′ biased in the saturation region in the activeperiod Tc. Therefore, the bias circuits 18 a and 18 b may be omitted.The sense amplifier 30 of this embodiment still can continuously biastransistors Tt1′ and Tt2′ to the saturation regions so that the cellcurrent Icell and the reference current Iref also become substantiallystable.

Fourth Embodiment

FIG. 8 is a circuit diagram showing a sense amplifier 40 according to afourth embodiment of the invention. As shown in FIG. 8, the differencebetween the sense amplifier 40 of the fourth embodiment and the senseamplifier 30 of the third embodiment is that the sensing node NDs isconnected to the node NDi1 of the latch circuit 16 via the switchcircuit SW1 and the reference node NDr is connected to the node NDi2 ofthe latch circuit 16 via the switch circuit SW2. The switch circuits SW1and SW2 may be switched such that the sensing voltage Vs on the sensingnode NDs and the reference voltage Vr on the reference node NDr may beisolated from the amplified voltages of the latch circuit 16.

Thus, the second to fourth embodiments also have the advantages similarto those of the first embodiment. That is, the sensing margin of thesense amplifier becomes larger, the data sensing accuracy becomeshigher, the values of the sensing current and the reference currentbecome substantially stable, and it is possible to prevent the detectionerror of the storage data due to the unstable values of the sensingcurrent and the reference current.

While the invention has been described by way of examples and in termsof preferred embodiments, it is to be understood that the invention isnot limited thereto. On the contrary, it is intended to cover variousmodifications and similar arrangements and procedures, and the scope ofthe appended claims therefore should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements and procedures.

1. A sense amplifier for sensing data stored in a memory cell of amemory, the sense amplifier comprising: a sensing node; a referencenode; a first bias circuit for biasing the sensing node to a firstvoltage in response to a first control signal; a second bias circuit forbiasing the reference node to the first voltage in response to the firstcontrol signal; a first transmission circuit for discharging the sensingnode via the memory cell; a second transmission circuit for dischargingthe reference node via a reference memory cell; and a latch circuit foramplifying a voltage difference between the sensing node and thereference node.
 2. The sense amplifier according to claim 1, furthercomprising: a third bias circuit, for biasing the sensing node to asecond voltage in response to a third control signal; and
 3. a fourthbias circuit, for biasing the reference node to the second voltage inresponse to the third control signal. The sense amplifier according toclaim 2, wherein the first, second and third control signals haveenabled levels respectively in a first period, a second period and athird period, the third period being between the first and secondperiods, and the first, second and third periods do not overlap with oneanother.
 4. The sense amplifier according to claim 2, wherein the firstand second transmission circuits respectively comprise: a firsttransistor having a first source/drain coupled to the sensing node, asecond source/drain for receiving the cell current and a gate forreceiving an enabled signal; and a second transistor having a firstsource/drain coupled to the reference node, a second source/drain forreceiving the reference current and a gate for receiving the enabledsignal, wherein the second voltage biases the first and secondtransistors to operate in saturation regions.
 5. The sense amplifieraccording to claim 1, further comprising: a first switch having a firstterminal coupled to the sensing node, and a second terminal coupled to afirst input terminal of the latch circuit, wherein the first switch isenabled in response to an enabled level of a fourth control signal toprovide a sensing voltage on the sensing node to the latch circuit; anda second switch having a first terminal coupled to the reference node,and a second terminal coupled to a second input terminal of the latchcircuit, wherein the second switch is enabled in response to the enabledlevel of the fourth control signal to provide a reference voltage on thereference node to the latch circuit.
 6. The sense amplifier according toclaim 5, wherein the first, second, third and fourth control signalshave enabled levels respectively in a first period, a second period, athird period and a fourth period, the fourth period being after thesecond period, and the first, second, third and fourth periods do notoverlap with one another.
 7. The sense amplifier according to claim 1,further comprising: a first capacitor having one terminal coupled to thesensing node and the other terminal for receiving a third voltage; and asecond capacitor having one terminal coupled to the reference node andthe other terminal for receiving the third voltage.
 8. The senseamplifier according to claim 1, wherein the latch circuit comprises: afirst inverter having a first input terminal, a first output terminaland a first power input terminal, wherein the first input terminal andthe first output terminal are respectively coupled to the sensing nodeand the reference node; a second inverter having a second inputterminal, a second output terminal and a second power input terminal,wherein the second input terminal and the second output terminal arerespectively coupled to the reference node and the sensing node; and afirst transistor having a first terminal for receiving a fourth voltageand a second terminal coupled to the first and second power inputterminals, wherein the first transistor is enabled in response to afifth control signal to provide the fourth voltage to enable the firstand second inverters.
 9. The sense amplifier according to claim 8,wherein the first and second inverters further respectively have a thirdpower input terminal and a fourth power input terminal, and the latchcircuit further comprises: a second transistor having a first terminalfor receiving a fifth voltage and a second terminal coupled to the thirdand fourth power input terminals, wherein the second transistor isenabled in response to a sixth control signal to provide the fifthvoltage to enable the first and second inverters.
 10. A data sensingmethod for sensing storage data stored in a memory cell of a memory, thedata sensing method comprising: biasing a sensing node and a referencenode to a first voltage in response to a first control signal;discharging the sensing node via the memory cell, and discharging thereference node via a reference memory cell; and enabling a latch circuitto amplify a voltage difference between the sensing node and thereference node.
 11. The method according to claim 10, furthercomprising: providing a sensing voltage on the sensing node and areference voltage on the reference node to the latch circuit throughswitches respectively.
 12. The method according to claim 10, furthercomprising: biasing the sensing node and the reference node to a secondvoltage in response to an enabled level of a second control signal.